This invention relates to a communication interface for a virtual IC tester.
An integrated circuit (IC) designer typically develops an IC design by creating an executable program that behaves in a desired way and is commonly referred to as a device logic simulator. The designer uses known techniques to convert the device logic simulator to an IC design that can be implemented in a physical IC device.
It is conventional to test a semiconductor integrated circuit device in order to determine whether it behaves as expected. A typical “per-pin” semiconductor integrated circuit tester includes multiple tester channels each capable of supplying a stimulus signal to an IC terminal or evaluating a response signal produced at that terminal. A typical IC tester is cycle based, i.e. it carries out a test in a succession of tester cycles. The start of a tester cycle is defined by an edge of a master clock signal. Prior to the start of a tester cycle, each tester channel receives (or internally generates) an instruction defining one or more states that the channel should assume for the tester cycle. A state may be NULL (no test activity) but otherwise the state defines a test event by specifying an activity that the channel is to perform during the tester cycle (e.g. FORCE HIGH, FORCE LOW, COMPARE HIGH, COMPARE LOW) and the programmable delay time (relative to the clock edge) at which the channel is to perform the specified activity. Thus, in one tester cycle a first tester channel might stimulate the device under test (DUT) by driving a first terminal of the DUT to a desired level at time t1 following the clock edge and a second tester channel might evaluate the response of the DUT to the stimulus by comparing the voltage level of the signal developed at a second terminal with a desired threshold level at a time t2 following the clock edge (where t1 and t2 are each less than the duration of the clock cycle). That particular tester cycle is then over and the test proceeds with another tester cycle.
The number of test events (force or compare) that can occur at a given pin during a given tester cycle is fixed and is typically in the range from one to four, depending on the particular tester.
A test engineer creates a test program that generates test data defining the state of each tester channel for each tester cycle having regard to the desired behavior of the device. Before employing the test program to control operation of a physical tester for testing a physical IC device, it is necessary to verify that the test data generated by the test program will appropriately test the device. This is done by using a virtual tester to test the device logic simulator.
The virtual tester is a program that receives the test data for a given tester cycle, and for each channel of the physical tester that is to perform a FORCE or COMPARE activity in that cycle, the virtual tester supplies parameter values representing the level (HIGH or LOW) of the FORCE or COMPARE activity and the programmable delay of the activity to the device logic simulator via a virtual tester interface. The device logic simulator carries out logic operations employing these parameter values and supplies parameter values representing the results of the COMPARE activities to the virtual tester via the virtual tester interface. The virtual tester interface is a communication interface that converts the parameter values provided by the virtual tester into a form acceptable to the device logic simulator and converts the result values provided by the device logic simulator to a form acceptable to the virtual tester. If the virtual tester determines that the device logic simulator behaved as expected, it implies that the test data is suitable for testing the physical device.
Traditional cycle-based testers are synchronous, in the sense that all the tester channels operate under control of the same master clock signal and all the test data is defined relative to a common tester clock rate. Conventionally, the virtual tester, the virtual tester interface and the device logic simulator are also tester cycle based, using the same tester rate. Thus, referring to FIG. 1, the virtual tester and the virtual tester interface operate under control of the master clock MCLK for receiving the test data, providing parameter values to the device logic simulator, and receiving the parameter values representing the device logic simulator's responses. The device logic simulator carries out its logic operations under control of the same master clock signal.
The conventional synchronous tester that has been described thus far is suitable for testing an IC device that has been designed so that all the circuit elements operate in response to a single clock signal. Such an IC device is said to have a single time domain. When the conventional tester is used to test a device having a single time domain, the tester is operated so that its cycle duration is equal to the period of the device clock signal.
Integrated circuit devices that are commercially available include devices that have multiple time domains. A first group of pins might be connected to circuit elements that operate in response to a master clock signal at a frequency FA and a second group of pins might be connected to circuit elements that operate in response to a master clock signal at a frequency FB. The group of circuit elements that operate in response to the clock signal at a given frequency are said to constitute a time domain of the device. The circuit elements that are connected to the first group of pins constitute time domain A and the circuit elements that are connected to the second group of pins constitute time domain B.
Some emerging testers support testing of IC devices having multiple time domains. In the case of an IC device having two time domains, as described above, the tester would typically employ a first group of tester channels connected to the first group of pins and a second group of tester channels connected to the second group of pins. The test activities conducted by the first group of channels take place in response to a first master clock signal and the test activities conducted by the second group of tester channels take place in response to a second master clock signal. Such a tester is considered to be asynchronous since there is no single tester cycle governing progression of the test activities at the terminals of all the channels. The test data is bounded to the different time domains, in that some portions of the test proceed at the rate of time domain A and other portions of the test proceed at the rate of time domain B.
Conventionally, the device logic simulator that is used to create an IC design having multiple time domains and to verify the test data for such an IC device is a single executable program that operates at a uniform rate of progression. Since there is no single tester cycle governing operation of the tester, the device logic simulator cannot run synchronously with the tester. It would in principle be possible to employ an asynchronous communication interface between an asynchronous virtual tester and the device logic simulator but the logic simulator would then have to deal with each time domain independently. Further, this approach would expose the specifics of the tester's architecture to the logic simulator. Thus, as new testers were developed, new virtual tester interfaces would be required. However, in order to preserve the value of a virtual tester interface that has been developed for a given device logic simulator, it is desirable that the virtual tester interface should not be dependent on the architecture of the virtual tester. Consequently, it is desirable to employ a synchronous communication interface between an asynchronous virtual tester and the device logic simulator for an IC device having multiple time domains.